VHDL stands for V ery high speed integrated circuit H ardware D escriptive L anguage. VHDL is a hardware descriptive language used to describe the behavior and structure of a digital system. Entity specifies the input and output of a particular device. Primary constants: Entity declaration. architecture body configuration declaration package declaration package body Rules: It is case insensitive. ex: a and A mean the same. half_adder and Half_ADDER are same. File name should always start with a alphabet '_' and other special characters can be used in file names The declaration include name,type of input and output. Entity declaration: Lets take an example, of half adder. sum is given by a xor b. and carry is given by a*b. entity declaration starts with the keyword entity. port is a keyword to specify input and output. input and output is represented as in bit or out bit. here bit is used to specify that it is one bit of informatio
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