VHDL

VHDL stands for Very high speed integrated circuit Hardware Descriptive Language.

VHDL is a hardware descriptive language used to describe the behavior and structure of a digital system.
Entity specifies the input and output of a particular device.

Primary constants:

• Entity declaration.
• architecture body
• configuration declaration
• package declaration
• package body

Rules:

• It is case insensitive. ex: a and A mean the same. half_adder and Half_ADDER are same.
• File name should always start with a alphabet
• '_' and other special characters can be used in file names
• The declaration include name,type of input and output.

Entity declaration:

Lets take an example, of half adder.

sum is given by a xor b.

and carry is given by a*b.

entity declaration starts with the keyword entity.

port is a keyword to specify input and output.

input and output is represented as in bit or out bit. here bit is used to specify that it is one bit of information. either level 1 or level 0.

example:

entity half_adder is

port ( a,b : in bit ; 

          sum,carry : out bit);

end half_adder ;

The above code is the entity declaration for half adder.

half_adder is the entity name chosen by the user.

at the end, end half_adder; is used to terminate the entity.

Note: keywords cannot be kept as file name.

Architecture body:

here architecture, of and is are keywords.

lets take the same example of half adder.

architecture HA of half_adder is

begin

sum <= a xor b;

carry <= a and b;

end HA;

here HA is the architecture name set by the user. of is a keyword used to indicate the entity.

architecture contains begin. and two or more begin can be present in the architecture.

note that for and operation, I have used a and b instead of a*b. because and is a predefined keyword.

end HA; is used to end the architecture.

Example: having entity declaration and architecture body.

program to find AND, OR, XOR, NOR, NAND.

solution:

entity gates is

port ( a,b : in bit ;

         and_g, or_g, xor_g, nor_g, nand_g : out bit);

end gate;

architecture all_gates of gates is

begin

and_g <= a and b;

or_g <= a or b;

xor_g <= a xor b;

nor_g <= a nor b;

nand_g <= a nand b;

end all_gates;